Altera Announces Agilex 2X, a Complete FPGA and SoC Portfolio
Posted by gmays 1 day ago
Comments
Comment by Foobar8568 1 day ago
That's not even a paper launch at this stage.
Comment by jacquesm 1 day ago
Comment by YakBizzarro 1 day ago
Comment by Foobar8568 1 day ago
Comment by ksec 1 day ago
My old perception was still based on pre AMD Xilinx era from 4-5 years ago and Xilinx was basically winning 60-70% market shares as Intel Altera was no where near competitive. ( As usual with any Intel acquisition)
Comment by Aromasin 1 day ago
They restricted wage growth too much for too long under Intel (despite being the only growing business unit), so the people with the valuable experience moved elsewhere. The Agilex line-up finally looks to be in the place it should have been 3 years ago, and it seems like they brought in a good marketing team following the Silverlake acquisition, but they still fall in this weird middle-ground now selling "performance-per-watt", which is a hard sell when most engineers optimise for the extremes. If I'm just need a bridge or some glue-logic, I don't need a device which will singe my thumbprints off while doing that. Generally, if you want better performance, AMD does an excellent job, or if you need low power consumption, Lattice is like 4 or 5x lower or more with just enough fmax and IO to be dangerous. If you look read Lattice's shareholder briefings, they're running away with the low/mid-range devices up to ~500k LUTs, and AMD is dominating anything 1M+. I couldn't help but laugh the other day when I saw an Intel reference design with a Lattice MachXO5-NX on it. Look at pretty much any datacentre rack now, and you'll spot 4-64 Lattice devices, when it used to be MAX10s top to bottom. Everything else is swept up by AMD.
For Altera, Agilex 9 (ADC and DAC converters integrated with an SoC FPGA) is probably their most interesting device, but that customer base is limited - basically comms and maybe radar with some weird and wonderful optical or quantum compute applications. I've heard friends of mine in the industry say very good things about it, but RF is not my strength so I can't comment.
In all honesty, they've got an insane fight on their hands to regain the market share. They canned their low end road-map when Sandra Riviera came in (as a classic Intel VP would do) and put all their eggs in the Agilex 7 basket for a long time. They've got Agilex 5 now (and Agilex 3, which is just the bottom SKUs of 5 with it painted over by marketing to fill the gap), which is great for vision applications, but only because they had a fantastic video and vision IP team who last I heard have left for ARM.
I hope they pull it back, as I loved the people there and it had a great culture, but it's been awfully mismanaged for a while and I question how easy it will be to pull it back considering the monopolies and duopolies that are appearing in the semi industry right now.
Comment by stn8188 1 day ago
Comment by duskwuff 22 hours ago
They're also competing with AMD's Zynq RFSoC line. I don't know how the two compare from a technology perspective, but AMD has a lot more mindshare.
Comment by Aromasin 19 hours ago
You want to be comparing it with Versal RF. Agilex 9 has about twice the bandwidth per channel, and keeps all the DSP in the fabric rather than hard blocks. Seems like it has very wide, instantaneous bandwidth and freq range in Ka-band. A few of my colleagues have jumped into startups building optical networking devices around them.
Comment by jpgvm 1 day ago
Comment by smallmancontrov 1 day ago
Comment by jpgvm 19 hours ago
On recent Agilex 7 the NoC exists but is fairly primitive and can only be used for DDR (and maybe HBM?) and it adds latency over direct pin access and has some other downsides that escape my memory right now.
The AMD FPGAs on the other hand have a very powerful and flexible NoC that runs both vertically and horizontally across the die and can be used to not just connect to hard IPs but also user logic across the die.
My hope is this new NoC is much more like AMD implementation, even if it can only do stuff like: Hard IP => Fabric => Hard IP as long as you can use it to connect F-Tile/R-Tile and not just DRAM that will be huge already in terms of saving massive amounts of fabric that otherwise gets eaten up by huge busses.
Comment by snvzz 1 day ago
I will always choose the vendors that do things properly, when they're even an option.
Comment by supaflybanzai 1 day ago
Comment by IshKebab 1 day ago
We're starting to see open source FPGAs but they are miniscule: https://tinytapeout.com/chips/ttihp26a/tt_um_fabulous_ihp_26...
Comment by dlcarrier 1 day ago
Comment by snvzz 1 day ago
Next best thing? The mature reverse-engineered families nextpnr[0] supports.
0. https://github.com/YosysHQ/nextpnrhttps://github.com/YosysHQ...
Comment by jauntywundrkind 1 day ago
Comment by aseipp 1 day ago
The reality is just that it's a lot of work, and Agilex is probably an order of magnitude (or two orders) more complex in scope than any existing FPGA with reversed or open specs. It's going to require a lot of expertise even with superhuman assistance. Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience. If people are going to Claude shit out in the EDA space I'd frankly rather have them work on more important day to day mundane things that are still lacking but important, eg improved performance, power analysis/floorplanning, sdc/constraint based clock synthesis and related tools, etc.
And yes, breaking your device is also a risk for some features too (eg Lattice ECP5 bitstream encryption has never been RE'd since it requires blowing fuses.) But the actual problem requires far more expertise than having Claude reverse engineer gameboy games.
Comment by duskwuff 22 hours ago
The terrible Fmax on GateMate is specifically a result of its "quirky" design. There's no dedicated clock network on the part - clocks have to be routed through fabric just like everything else. Running those signals everywhere consumes routing capacity and incurs delays; the resulting clock skew is awful.
Comment by imtringued 9 hours ago
Comment by omegaSigma95 1 day ago
Comment by logicallee 1 day ago