NLnet announces funding for 67 more open-source projects
Posted by laurenth 9 hours ago
Comments
Comment by ggm 9 hours ago
Thaler presumably winds up having to have a clearing house function, which is a public utility question: Maybe NLNet foundation is thinking about the long history of the dutch engagement in fintech, back to the 17th century?
Comment by em-bee 9 hours ago
Comment by csomar 5 hours ago
Comment by ggm 5 hours ago
On reviewing who is on it, I know several members of the board. I would not call them "nerds" in the pejorative sense they're serious people with decades of experience in the ICT sector. If you didn't mean it disparagingly, they are certainly nerdy, but they are not only a "bunch of nerds"
Comment by fsckboy 3 hours ago
the sentence you are referring to said (pay attention to the italics): "I don’t think they represent either the EU or Netherlands position when it comes to privacy.
Comment by ggm 3 hours ago
Comment by menaerus 44 minutes ago
Comment by rnijveld 6 minutes ago
Comment by benterix 12 minutes ago
Comment by VitaSetLLC 8 hours ago
Also the Vita FPGA Architecture Logic and Memory Blocks are bug-free.
Comment by VitaSetLLC 6 hours ago
1. Proposal Description:
The Vita FPGA Architecture Subproject is licensed under The VitaSet License.
The VitaSet License is a permissive license which does not offer any implied warranties and patent grants and does not require the inclusion of this license's text on binary and hardware forms of the source code that is licensed under this license.
This is to prevent executables and computer chips from wasting resources on including license text, but for source code to keep copyright attribution, so that when source code access gets interrupted, no claim of copyright infringement can be made towards the developers, as the claimant would have the copyright header of this license.
The Vita FPGA Architecture Verilog files VitaFPGAArchLogicBlock.v and VitaFPGAArchMemoryBlock.v are bugfree.
Any Vita FPGA Architecture Logic Block can act as though it is an Vita FPGA Architecture Interconnect Block. Thus, any possible truth-table can be expressed with enough Vita FPGA Architecture Logic Blocks, Vita FPGA Architecture Interconnect Blocks and Vita FPGA Architecture Memory Blocks. Thus, any integrated circuit could run on the Vita FPGA Architecture, given enough Vita FPGA Architecture Logic Blocks, Vita FPGA Architecture Interconnect Blocks and Vita FPGA Architecture Memory Blocks are available.
2. Proposal Title: Vita FPGA Architecture Chip and Toolchain Investment Proposition
3. Former Contributions to the Open Source Space: I am the Founder and CEO of VitaSet LLC.
4. Former and current financial beneficiaries of your project, if any: Over $400 have been donated by my relatives to me during late 2023. No other funds have been raised.
5. Are there any open source projects that are similar to yours? List any that you know of that exist. https://github.com/efabless/clear - The Open Source FPGA ASIC. A open source Apache 2.0 eFPGA + VexRiscV CPU Chip that only sold a couple hundred physical computer chips before they stopped selling anymore through Tiny-Tapeout. I did not read their source code, my Vita FPGA Architecture was designed exclusively by me entirely from scratch. I have however read the GitHub Issues of the Clear FPGA Project and I see someone asking about the bugginess of the reset circuitry. My Vita FPGA Architecture is bug-free and permissively licensed under an open source license.
6. What Technical Challenges has your project overcome and might overcome in the future? List all that apply. Reducing the environmental waste caused by upgrading computer hardware, as simple software updates can be issued to update the FPGA Bitstreams instead of manufacturing new physical computer chips.
Also, people can take advantage of the Vita FPGA Architecture to code up and use Hardware Accelerated Programs when computer chip transistors stop getting smaller.
7. How compatible is your open source project with the open source ecosystem? The Vita FPGA Architecture is synchronous clocked logic with an synchronous reset, so unlike the incompatibility of asynchronous integrated circuits, it will be compatible with the synchronous clocked ecosystem of commercial integrated circuits.
8. Upload your PGP Key (optional): https://github.com/VitaSetLLC/VitaSet-LLC-Asymmetric-Cryptographic-Public-Key
Edit: No A.I. was used by me.Comment by 6_7 7 hours ago
Comment by em-bee 9 hours ago
i have difficulty to judge whether this project is suitable for a grant, and i don't know how much effort it takes to apply and whether i can afford to spend that time instead of focusing on finding other paid work.
Comment by andai 9 hours ago
(Also it looks like most of the repos haven't been touched in a long time. Which repo is relevant?)
Comment by dannyobrien 9 hours ago
Comment by Sean-Der 6 hours ago
I am grateful the code got written, but even better people got careers out of it/learned new stuff. If you are on the fence about taking on a project I encourage you to do it!
Comment by Multicomp 9 hours ago
Comment by jbverschoor 9 hours ago
Comment by toppigamer 9 hours ago
Comment by greatgib 7 hours ago
If you look "how to apply they say": We've kept the application form short so as not to waste your time.
They you see the form... https://nlnet.nl/propose/
ok, getting thousands of euros deserve a little bit of paperwork, but let's not call that form "short".
But what triggered me is the following field of the form: Which model did you use? What did you use it for? Please submit the dates of the prompts, the prompts themselves and the unedited output in this text field.
Then you can see the "AI" policy that is attached: https://nlnet.nl/foundation/policies/generativeAI/
And in my modest opinion, that is another perfect example of the bureaucratic stupidity nightmare.
I would understand to ask details about your intended usage of LLMs for the project. Also to ensure that LLMs is only used as an assisting tool but not to do the work autonomously.
But imagine listing the "dates" and "prompts" that you used, for example to ask the llm to correct your badly written sentences to fill the stupid fields of their form?
And then, recording every time you used a LLM (coding or not) for whatever for the project... Assuming that the recipient of the grant will not lie anyway. This record doesn't give any proof that the code is not "stolen", "copied", or "contaminated".
Just have the delivery evaluated. Independently or by the project receiving the change. Judge on results for once instead of getting orgasms based on the paperwork trail. In the end, why should we care if the author had to use a LLM, a code editor, a spreadsheet, a marabout, or whatever else? If we can confirm that the result is there, in satisfactory condition (clean and safe code, good performance, ...) and without apparent "copyright violation".
Comment by a2128 4 hours ago
Also, the prompts and dates is for writing the grant proposal itself, and not for coding. Maybe they receive too many AI generated proposals. It feels rather rude anyway to be asking for 5,000 to 50,000 euros funding for your project if you can't even fill in the six free-form fields yourself.
Comment by greatgib 1 hour ago
I don't see why it ,would be rude. Only if the proposal is of bad quality!
Comment by nairboon 1 hour ago